1. Field of the Invention
The present invention relates to a semiconductor memory device. More specifically, the present invention relates to a technique for driving a word line.
2. Description of the Related Art
In the field of a semiconductor memory device having a plurality of memory cells, a plurality of word lines and a plurality of bit lines, the following techniques are known as conventional techniques for driving the plurality of word lines, for example.
Japanese Laid-Open Patent Application (JP-A-Heisei, 7-169282) discloses a nonvolatile semiconductor memory device. In the nonvolatile semiconductor memory device, a circuit that drives a word line is constituted by an inverter circuit that includes an n-channel transistor and a p-channel transistor. A block select address signal generated from a first address signal group is supplied to a source line of each of the transistors. In addition, a gate select address signal generated from a second address signal group is supplied to a gate of each of the transistors.
Japanese Laid-Open Patent Application (JP-P2000-113689) discloses a row decoder used in a nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device has a hierarchical word line structure and includes main word lines and local word lines. The row decoder includes a first transistor of PMOS type and a second transistor of NMOS type. One of conduction terminals of the first transistor is connected to a main word line, and the other is connected to a local word line. One of conduction terminals of the second transistor is connected to a local word line, and the other is connected to a ground power supply line.
FIG. 1 schematically shows a configuration of a conventional semiconductor memory device. In particular, FIG. 1 shows a configuration of a circuit for driving a word line. The semiconductor memory device has a hierarchical word line structure, namely, includes main-word lines and sub-word lines. An “SWD” (sub-word driver; sub-word decoder) 120 is a circuit for driving a corresponding sub-word line, and applies a driving voltage to the corresponding sub-word line. The driving voltage is supplied from an internal power supply circuit 130 to each SWD 120.
The internal power supply circuit 130 includes a read voltage generating circuit (RCP) 131, a write voltage generating circuit (ACP) 132, a plurality of first power supply switches (PWS_G) 160, and a plurality of second power supply switches (PWS_H) 170. The read voltage generating circuit 131 and the write voltage generating circuit 132 are charge pumps. The read voltage generating circuit 131 and the write voltage generating circuit 132 are connected to the plurality of first power supply switches 160_0 to 160_g. One first power supply switch 160 _i (160 _0 to 160_g) is connected to a plurality of second power supply switches 170_i0 to 170_ih through a first power supply interconnection VXPG_i. One second power supply switch 170_ij (170_i0-170_ih) is connected to one sub-word driver 120_ij through a second power supply interconnection VXPG_ij.
The read voltage generating circuit 131 and the write voltage generating circuit 132 supply respective of a read voltage VPRG and a write voltage VPPG to the plurality of first power supply switches 160_i. Each of the first power supply switches 160_i supplies a power supply voltage VCC, the read voltage VPRG and the write voltage VPPG to the first power supply interconnection VXPG_i in a standby state, a read operation and a write operation, respectively. The second power supply switches 170_ij supplies the voltage received through the first power supply interconnection VXPG_i to the second power supply interconnection VXPG_ij in response to a block address select signal. As a result, the read voltage VPRG or the write voltage VPPG is supplied as the driving voltage to the sub-word driver 120_ij connected to a selected memory cell block.
FIG. 2 is a circuit diagram showing a configuration of the sub-word driver (SWD) 120 according to the conventional technique. The sub-word driver 120 includes a level shifter 140 and a plurality of final stage drivers 150_0 to 150_k. The level shifter 140 includes P-channel transistors 141 and 142. Sources 141s and 142s of the respective P-channel transistors 141 and 142 are connected to the second power supply interconnection VXPG_ij. When a control signal MXCNT is turned on and the main-word line MX connected to the sub-word driver 120 is selected (is changed to Low level), a source voltage of the P-channel transistor 142 is output from the level shifter 140.
The plurality of final stage drivers 150_0 to 150_k, which are connected to a plurality of sub-word lines SX0 to SXk, drive the plurality of sub-word lines SX0 to SXk, respectively. More specifically, each of the final stage drivers 150_0 to 150_k includes transistors that constitute an inverter. Gates of the transistors are connected to any one of pre-word lines PX0 to PXk. Also, a source of a P-channel transistor 151 of the transistors is connected to the output of the level shifter 140. Therefore, when one of the pre-word lines PX0 to PXk is selected (is changed to Low level), a source voltage of a corresponding one P-channel transistor 151 is supplied to a corresponding sub-word line SX. Namely, the driving voltage (read voltage VPRG or write voltage VPPG) supplied from the second power supply interconnection VXPG_ij is applied to the selected sub-word line SX.
Also, the above-mentioned second power supply interconnection VXPG_ij is connected to back gates 141b and 142b of the respective P-channel transistors 141 and 142 of the level shifter 140, and to back gates 151b of the respective P-channel transistors 151 of the final stage drivers 150. More specifically, the voltage (read voltage VPRG or write voltage VPPG) of the second power supply interconnection VXPG_ij is applied to a well SWDPW in which those P-channel transistors 141, 142 and 151 are formed. In this manner, the sources (141s, 142s) and the back gates (141b, 142b) of the P-channel transistors 141 and 142 of the level shifter 140 are controlled by the same power supply line VXPG_ij.
FIG. 3 is a timing chart showing a word line driving operation performed by the above-mentioned semiconductor memory device. At time t0, the semiconductor memory device is powered, and a supply of power supply voltage VCC is started. Accordingly, the read voltage generating circuit 131 is activated to start supplying the read voltage VPRG. Thereafter, the first power supply switch PWS_G supplies the power supply voltage VCC to the first power supply interconnection VXPG_i, and the second power supply switch PWS_H supplies the ground voltage GND to the second power supply interconnection VXPG_ij. That is to say, in a standby state, the voltages of the sources and back gates of the P-channel transistors 141 and 142 in the sub-word driver 120 are maintained at the ground voltage GND.
A read access operation is as follows. At time t1, a chip select signal CS and a block address select signal ADD are input. The input signals are detected by an address transition detection circuit (not shown), and a power supply switch activation signal ATDX is enabled at time t2. Thereby, the first power supply switch (PWS_G) 160 and the second power supply switch (PWS_H) 170 associated with the selected memory cell block are activated. At time t3, the voltage of the first power supply interconnection VXPG_i starts rising to the read voltage VPRG. Accordingly, the voltage of the second power supply interconnection VXPG_ij starts rising to the read voltage VPRG. As a result, the sources 141s and 142s of the respective P-channel transistors 141 and 142 in the sub-word driver 120 and the well SWDPW are charged.
Then, in response to a word line select signal, the corresponding main-word line MX and pre-word line PX are driven to the Low level. As a result, the read voltage VPRG is output from the level shifter 140, and the read voltage (driving voltage) VPRG starts to be supplied to one sub-word line SX designated by the word line select signal. In the example shown in FIG. 3, the voltage of the designated sub-word line SX rises from the ground voltage GND to the read voltage VPRG from time t4 to time t5.
After that, at time t6, the input of the chip select signal CS and the block address select signal ADD is finished. The voltage of the second power supply interconnection VXPG_ij thereby starts falling from the read voltage VPRG to the ground voltage GND. In this case, the voltage of the well SWDPW that has been charged with the read voltage VPRG also starts falling to the ground voltage GND. At time t7, the voltage of the designated sub-word line SX starts falling, and then the driving of the sub-word line SX is finished.